Lattice Releases 2nd Generation SuperBIG CPLD Architecture for System-level Integration

ispMACH 5000VG ISP CPLDs Complete Lattice's BFW II Products

HILLSBORO, Ore.--(BUSINESS WIRE)--Nov. 12, 2001--Lattice Semiconductor Corporation (Nasdaq:LSCC - news) today announced the immediate availability of the first device in its ispMACH® 5000VG SuperBIG(TM) CPLD family, the 1024 macrocell ispMACH 51024VG device.

This in-system programmable (ISP(TM)) logic family, which provides double the logic capacity of the popular ispLSI® 5000VE family, includes new features such as advanced I/O standard sysIO(TM) support and sysCLOCK(TM) Phase Locked Loops (PLLs) to meet next generation system design needs.

Performance for the first device, the ispMACH 51024VG, is specified at 5ns pin-to-pin logic delays (tPD) with an operating frequency (fMAX) of 178 MHz, world-class performance for a device of this density. The release of this family represents the completion of Lattice's second generation of BFW (Big-Fast-Wide) products, consisting of the 3.3V power supply ispMACH 5000VG, ispLSI 2000VE and ispLSI 5000VE families.

"The ispMACH 5000VG is the result of extensive collaboration between Lattice's silicon and software designers," said Stan Kopec, Vice President of Corporate Marketing at Lattice. "It represents a new class of SuperBIG CPLD with system-level integration and features that still provides traditional CPLD ease-of-design, performance and non-volatile, 'instant-on' capability."

The devices from the ispMACH 5000VG family incorporate a SuperWIDE(TM) macrocell architecture pioneered in Lattice's ispLSI 5000V family. Logic capacities beginning at 768 macrocells are large enough to hold multiple functions commonly implemented in CPLDs such as bus bridges, memory controllers, and control logic. The large number of sysIO-capable pins (from 196 to 384 per device) provided in the ispMACH 5000VG devices makes them ideal for wide bus interface applications. The instant power-up capability of these devices makes them suitable for power-up sequence control in large, complex systems.

sysIO Capability for Board-Level Performance

Each I/O pin on the ispMACH 5000VG devices can be configured to support high-speed memory interfaces, advanced bus standards, or general-purpose interfaces. General-purpose interface support includes LVTTL or LVCMOS (3.3, 2.5 & 1.8 Volts). The LVTTL and LVCMOS 3.3 interfaces are 5-Volt tolerant, supporting easy integration into legacy designs. Programmable drive levels for these standards facilitate the elimination of series termination resistors, reducing overall system cost.

Interface to high speed DRAMs, SRAMs, and other high performance memory devices is made possible with SSTL2, SSTL3, and HSTL I/O support. The ispMACH 5000VG family also supports GTL+, PCI, and PCI-X I/O configurations for use in high-speed bus interfaces.

sysCLOCK PLLs For Timing Control

The ispMACH 5000VG devices have two sysCLOCK PLLs that provide precise timing control for today's high-speed designs. Designers can generate complex clock waveforms with the clock multiply and divide capability of the PLL as well as adjust setup, hold and clock to output timings by shifting the clock under sysCLOCK control.

SuperBIG Tiered Routing for Higher Densities

The ispMACH 5000VG family takes CPLD logic densities to new highs through its tiered routing architecture. Utilizing its industry-leading non-volatile E2CMOS® technology, Lattice provides devices of up to 1024 macrocells using this new architecture that conserves silicon area while maximizing performance.

SuperWIDE Logic Blocks for High Performance

This family uses the proven SuperWIDE 68-input logic block that is found in other ispLSI 5000 devices, providing excellent support for emerging 64-bit applications. Lattice has found that for complex functions this SuperWIDE capability leads to a 60% performance gain compared to devices with the more traditional 36-input logic block. Additionally, Lattice enhanced the ispMACH 5000VG logic block by increasing the maximum number of product terms per function from the 35 implemented in the ispLSI 5000VE series to 160. This leads to further performance improvements, up to 25% faster than architectures that support a maximum of 35 product terms per function.

Design Tools

The ispMACH 5000VG family is supported by Lattice's new ispLEVER(TM) Version 1.0 design tools. The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance and features of the ispMACH 5000VG devices while maximizing resource utilization. This is achieved through timing driven placement & routing coupled with optimized synthesis support from vendors such as Exemplar and Synplicity. Lattice customers with valid software maintenance agreements will be upgraded to the new software suite during the first quarter of 2002.

Price and Availability

The ispMACH 51024VG is available now in 484- and 676-ball fine pitch Ball Grid Array (BGA) packaging featuring a space-saving 1 millimeter ball pitch. Projected pricing for the ispMACH 51024VG is as low as $50.00 in high-volume for the second half of 2002.

About Lattice Semiconductor

Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISP(TM) programmable logic devices (PLDs) and offers total solutions for today's advanced logic designs.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503/268-8000, FAX 503/268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, L (& design), Lattice (& design), in-system programmable, ispLEVER, SuperBIG, SuperWIDE, ispMACH, ispLSI, sysCLOCK, sysIO, E2CMOS, ISP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

     Lattice Semiconductor Corporation, Hillsboro
     Sean Hildenbrand, 503/268-8680
     Sean.hildenbrand@latticesemi.com